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4M x 32 -Bit Dynamic RAM Module SMALL OUTLINE MEMORY MODULE
HYM 324020GD(L)-50/-60
Preliminary Information
* * *
72-Pin Small Outline Dual-in-Line Memory Module 4 0194 034 words by 32-bit organization Performance:
tRC tRAC tCAC tAA tPC Read / Write Cycle Time RAS Access Time CAS Access Time Access Time From Address Fast Page Mode Cycle Time -50 90 50 13 25 35 -60 110 60 15 30 40 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3 V) supply Low power dissipation max. 2880 mW active (-50 version) max. 2592 mW active (-60 version) LVTLL - 57.6 mw standby LVCMOS- 28.8 mW standby LVCMOS- 5.76 mW standby (L-version)
* * * * * * * * * *
Fast Page Mode Low Power Versions with Self Refresh CAS-before-RAS refresh, RAS-only-refresh 8 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible Utilizes eight 4M x 4 -DRAMs in TSOPII-packages Card size 56.69mm x 25.40mm x 3.80 mm 12 / 10 Adressing (Row/Column) 4096 refresh cycles / 64 ms Gold contact pad
Semiconductor Group
1
2.96
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
The HYM 324020GD(L) -50/-60 are 16 MByte DRAM 72pin small outline dual-in-line memory modules organized as 4M x 32, comprising eight HYB3116400BT(L) 4M x 4 DRAMs in 300 mil wide TSOPII-26/24 - packages mounted together with eight 0.2 F ceramic decoupling capacitors on a PC board. These modules are optimized for use in byte-write non-parity applications. Each HYB 3116400BT(L) is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The density and speed of the module can be detected by the use of presence detect pins. These modules are ideal for portable systems applications where high memory capacity is needed. Ordering Information Type HYM 324020GD -50 HYM 324000GD -60 HYM 324020GDL -50 HYM 324000GDL -60 Pin Names A0-A11 A0-A9 DQ0 - DQ31 RAS0, RAS2 CAS0 - CAS3 WE Vcc Vss PD1 - PD7 N.C. Presence-Detect Truth Table *): Module HYM 324000GD -50 HYM 324000GD -60 HYM 324000GDL -50 HYM 324000GDL -60 *) note: PD1...PD4 PD5..PD6 PD7 PD1 NC NC NC NC PD2 NC NC NC NC PD3 VSS VSS VSS VSS PD4 NC NC NC NC PD5 VSS NC VSS NC PD6 VSS NC VSS NC PD7 NC NC VSS VSS Row Address Input Column Address Inputs Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Power (+3.3 Volt) Ground Presence Detect Pins No Connection Ordering Code Package L-DIM-72-3 L-DIM-72-3 L-DIM-72-3 L-DIM-72-3 Descriptions 50 ns DRAM module 60 ns DRAM module 50 ns Low Power DRAM module 60 ns Low Power DRAM module
: configuration : speed : refresh mode
Semiconductor Group
2
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
Pin Configuration
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35
Name VSS DQ1 DQ3 DQ5 DQ7 PD1 A1 A3 A5 A10 DQ8 DQ10 DQ12 DQ14 A11 A8 NC DQ15
PIN 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
NAME DQ16 VSS CAS2 CAS1 NC WRITE DQ18 DQ20 DQ22 NC DQ25 DQ28 VCC DQ30 NC PD3 PD5 PD7
PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
NAME DQ0 DQ2 DQ4 DQ6 VCC A0 A2 A4 A6 NC DQ9 DQ11 DQ13 A7 VCC A9 RAS2 NC
PIN 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
NAME DQ17 CAS0 CAS3 RAS0 NC NC DQ19 DQ21 DQ23 DQ24 DQ26 DQ27 DQ29 DQ31 PD2 PD4 PD6 VSS Pin2 Pin1
Pin72
Pin71
Front Side
Back Side
Semiconductor Group
3
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
RAS0 CAS0 DQ0-DQ3 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D1
DQ4-DQ7 CAS1 DQ8-DQ11
CAS RAS I/O1-I/O4 OE D2 CAS RAS I/O1-I/O4 OE D3
DQ12-DQ15
RAS2 CAS2 CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D5
DQ16-DQ19 DQ20-DQ23
CAS3 CAS RAS I/O1-I/O4 OE D6 CAS RAS I/O1-I/O4 D7 OE
DQ24-DQ27 DQ28-DQ31
A0R-A11R A0C-A9C WE
D0-D7 D0-D7 D0-D7
VCC VSS
C0 - C7
Block Diagram
Semiconductor Group
4
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 0.2 10 10 2.0 - 0.3 2.4 - Vcc-0.2 - 10 - 10
Unit Note V V V V V V A A 1) 1) 1) 1) 1) !)
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
-50 ns version -60 ns version
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Average Vcc supply current:
- -
800 720 16
mA mA mA
2) 3) 4) -
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
ICC2
-
ICC3 Average Vcc supply current, during RAS-only refresh cycles: -50 ns version -60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
- -
800 720
mA mA
2) 3)
Semiconductor Group
5
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Symbol Limit Values min. max. 320 280 8 1.6 mA mA mA mA 2) 3) 4) - - Unit Note
Average Vcc supply current, during fast page mode:
ICC4
-50 ns version -60 ns version
- -
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5
- -
Standby Vcc supply current (L-version)
(RAS=CAS= Vcc-0.2V)
ICC6 Average Vcc supply current, during CAS-beforeRAS refresh mode: -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
- - -
800 720 2
mA mA mA
2) 4)
Self Refresh Current (L-version only)
CBR cycle with RAS>tRASS(min.); CAS held low; WE=Vcc-0.2V; Addresses and Di=Vcc-0.2V or 0.2V
ICC7
Capacitance TA = 0 to 70 C, VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,WE) Input capacitance (RAS0, RAS2) Input capacitance (CAS0 - CAS3) I/O capacitance (DQ0-DQ31) Symbol Limit Values min. max. 55 40 25 15 pF pF pF pF - - - - Unit
CI1 CI2 CI3 CIO
Semiconductor Group
6
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
Limit Values -50 min. max. - - 10k 10k - - - - - 37 25 min. 110 40 60 15 10 0 10 0 15 20 15 15 60 - 50 64 256 5 3 - - -60 max. - - 10k 10k - - - - - 45 30 - - - 50 64 256
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period (L-version) tRC tRP tRAS tCAS tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF 90 30 50 13 10 0 8 0 10 18 13 13 50 5 3 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
Limit Values -50 min. max. - - - - - - - min. 10 10 0 15 15 0 10 -60 max. - - - - - - -
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 10 ns ns ns ns ns ns ns 14 14 13
Fast Page Mode Cycle
Fast page mode cycle time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCPA tRAS tRHCP 35 - 50 30 - 30 200k - 40 - 60 35 - 35 200k - ns ns ns ns 7
CAS-before-RAS refresh cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Self Refresh Cycle (L-version only)
RAS pulse width RAS precharge time CAS hold time tRASS tRPS tCHS 100k 95 -50 _ _ _ 100k 110 -50 _ _ _ ns ns ns
Semiconductor Group
8
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels . 13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle. 14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM324020GD(L)-50/-60 4M x 32 SO-DIMM
SO-DIMM PACKAGE OUTLINES
56.69 3.8 max FRONT SIDE
17.78
1 E 44.45 7.62 8.255 51.66 2 R 2.0
71
25.40
5.0 min.
1.0 +/- 0.1 R 2.0
72
BACK SIDE 1.0 note: mechanical key for supply voltage 5 V E = 6.35 3.3V E = 3.175
1.27
Preliminary Drawing L-DIM-72-3
Semiconductor Group
10

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